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6 – Testbench Operation and Modification
Verification Testbench
Microsemi has developed a 1553B verification testbench ( Figure 6-1 ) that you can use to verify core
performance per the 1553B specification. The testbench is coded in VHDL and contains four Core1553B
remote terminals connected to a bus control function and backend interfaces. A procedural testbench
controls the various blocks and implements the tests. The source code is not made available with
Obfuscated licenses of the core.
Backend
CW
Legality
Backend
CW
Legality
Backend
CW
Legality
Backend
CW
Legality
Core1553B
RT 0
Core1553B
RT 1
Core1553B
RT 2
Core1553B
RT 3
Procedural
1553B
TCV
TCV
TCV
TCV
TCV
TCV
TCV
TCV
Testbench
1553B Busses
Bus Control
(encoder and decoder)
Bus Control
(encoder and decoder)
Bus
Monitor
Bus
Monitor
Figure 6-1 ? Verification Testbench
The testbench includes four RTs to test core variants, each with different setups of the core configuration
inputs ( Table 6-1 ).
Table 6-1 ? Verification Testbench RT Configuration
RT
0
1
2
3
Clock Speed
Variable
16 MHz
16 MHz
16 MHz
Memory Interface
Asynchronous
Synchronous
Asynchronous
Synchronous
Command Word Legality*
Internal
Internal
Internal
External
Note: *All command word legality interfaces are external for Obfuscated simulation.
The testbench uses a command word legality module that disables subaddresses 26 and 27 for transmit
commands. For receive commands, subaddress 25 is disabled, and subaddress 27 is only enabled for
Revision 3
37
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